Many modern devices may include a system on a chip (SoC) with multiple cores. Traditionally, the multiple cores are identical to each other. Such cores can include millions of logic gates. In order to test such a large number of logic, each core may include its own compression macro, e.g., a compressor-decompressor (CoDec). The decompressor portion of the CoDec decompresses the received test data and the compressor portion compresses the responses of the applied test data. Further, each of the cores of the SoC receives the same test data. Also, one or more cores can be tested at a time.
If only one core of the SoC is tested at a time, the other cores remain inactive. As such, during the test of the active core, the CoDec will (i) decompress the test data received at the scan in (SI) of the SoC and (ii) output the compressed responses to the scan out (SO) of the SoC. However, if more than one core is tested, a compactor is required to compact the compressed responses from each of the cores before they are output to the SO. One way to compact the compressed responses from the multiple cores is to assign each ith output of a core to a corresponding ith exclusive OR (XOR) logic gate of the compactor. Accordingly, the ith output of any core will be XORed with the respective ith outputs of the other cores. This configuration is known as symmetric assignment.
One of the benefits of symmetric assignment is an inherent X-tolerance. “X-states” (e.g., unknown logic states) can occur for a variety of reasons, such as: (1) the automatic test pattern generation (ATPG) cannot accurately model certain logic modules and the un-modeled logic gets captured at a scan element (e.g., scan flip-flop), (2) internal three-state logic that could go to high-Z (i.e., high impedance), (3) uninitialized non-scan flip-flop/latches that cannot be reset prior to scan test application, (4) unknown RAM output (e.g., output of RAM may be unknown if not all of the RAM bits have time to get to logical “0” after a chip powers on), (5) a third-party vendor does not provide enough data to determine all of the possible outputs after a chip is powered on and, thus, X-states have to be assumed for the undetermined outputs, (6) some of the gates being tested are fed by analog logic (i.e., which does not use logical “1s” and “0s”), and (7) at-speed delay tests in which not all of the paths can meet the desired timings. Further, a single X-state found within a compression environment will likely combine with other non X-states (i.e., known values) and, thus, corrupt those values before they can be observed at the output of the compression. As such, as the X-states are shifted through the compression logic, the compression efficiency will be adversely affected, resulting in a higher pattern count and lower test coverage. With symmetric assignment, because the cores are identical to each other, the X-states can be isolated to a specific XOR logic gate of the compactor.
However, the symmetric assignment configuration can also lead to the masking of multiple identical faults. For example, assuming an ith output of each of the cores outputs a “0” (e.g., associated with a faulty response) or a “1” (e.g., associated with a good response), if there are an even number of cores and all of them have an identical fault, the output of the corresponding ith XOR logic gate will be a “0” in both scenarios (e.g., all “0” inputs or all “1” inputs). As such, it will be unknowable if the corresponding device is faulty or not.
Accordingly, there is a need for an efficient top-level compactor for a SoC with multiple identical cores, which is both X-tolerant and can handle multiple identical faults.